The High definition television (HDTV) standard adopted by the Advanced Television Systems Committee (ATSC) in the U.S. is described in the “ATSC Digital Television Standard”, Document A/53 published on Sep. 16, 1995. This document sets forth all the requirements regarding HDTV signal characteristics. In particular, the ATSC-HDTV signals require a suppressed carrier vestigial sideband modulation format, which is a well-known amplitude modulation method. In addition, a small in-phase pilot at the suppressed carrier frequency is added to the signal, being 11.3 dB below the average signal power.
A typical ATSC-VSB receiver demodulating scheme is disclosed in U.S. Pat. No. 6,233,295 entitled SEGMENT SYNC RECOVERY NETWORK FOR AN HDTV RECEIVER issued on May 15, 2001 to Wang. The disclosed demodulator includes an analog to digital (A/D) converter sampling at 21.52 MHz, a carrier tracking loop (CTL) operating at the 21.52 MHz sampling rate, followed by a symbol timing loop (STL) operating at the 10.76 MHz symbol rate, followed by a sync detector, equalizer and phase tracker (i.e., phase tracking loop), all working at the symbol rate of 10.76 MHz.
The A/D converter samples the analog signal at the sampling frequency, converting it into a sequence of digital samples with a specified number of bits per sample.
Carrier tracking, which is performed by the CTL, addresses the problem of frequency offset between the transmitter and receiver oscillators either intrinsic to their design or due to drifts, causing a drift of the sinusoidal carrier signal. The offset will cause the received signal constellation to rotate and forbid signal recovery. This “spinning” effect must be removed before accurate symbol decisions can be made. The purpose of the carrier tracking loop (CTL) is to remove this frequency offset and demodulate the signal down to baseband (from the original IF or near baseband frequency), so that the received signal can be properly processed directly at baseband. In the case of the VSB transmitted signal, by frequency shifting the signal down to baseband the full signal spectrum can be recovered from the RF spectrum, since only a portion of the original spectrum is actually transmitted.
Timing recovery, which is performed by the STL, is the process by which the receiver clock (timebase) is synchronized to the transmitter clock by decoding the timing signal which is embedded in the transmitted VSB signal. The two quantities which the receiver must determine in order to achieve symbol synchronization are the sampling frequency and the sampling phase. The sampling frequency is typically specified but oscillator drift will introduce deviations from the stated symbol rate. Sampling phase involves determining the correct time within a symbol period during which to take a data sample. The accuracy of the recovered timing signal is substantially equivalent to the accuracy of the transmitted VSB timing signal.
The sync detector detects the field and segment sync information embedded in the data stream by correlation and provides this information to other receiver blocks for synchronization purposes.
Equalization is a signal processing technique that attempts to correct for linear distortions in the received signal, which appear in the form of ISI, mainly caused by channel impairments (e.g., multipath propagation in the terrestrial broadcast channel) or by filtering in the receiver or transmitter.
Because the CTL is relatively narrow band, it cannot track high frequency phase noise (jitter) present in the carrier. This phase jitter manifests itself as a rotation of the symbol constellation in the complex plane. For this reason, a separate phase tracking loop (PTL), operating on the channel equalized baseband signal, is provided in the receiver to derotate the signal constellation so that symbol decisions will be accurate. Such PTLs are decision directed. That is, they calculate the phase difference between the phase of each received constellation point and the phase of the ideal constellation point corresponding to the symbol decided to be the most likely symbol to have been transmitted. This phase difference is then used to control the derotation of the baseband signal, all in a known manner. Because the system is already frequency locked to the carrier by the CTL, the PTL bandwidth is maximized for phase tracking by using a first order loop.
FIG. 1 is a block diagram of such a prior art phase tracking loop for use in an ATSC-HDTV television broadcast communications system. In FIG. 1, the received symbols are represented by a multilevel signal modulated as a VSB signal. More specifically, such a signal can be a suppressed-carrier 8-VSB, 15-VSB or 16-VSB modulated signal.
In FIG. 1, an input terminal 5 is coupled to a receiver front end (not shown) producing an equalized baseband signal representing successive transmitted symbols. The receiver front end may include, for example, an RF tuner, an IF amplifier, an analog-to-digital converter, a digital carrier recovery circuit, a symbol clock recovery circuit, a DC compensation circuit, a field and segment synchronization signal detector, an NTSC co-channel interference rejection circuit, and an adaptive channel equalizer, all of known design and most of which have been described above.
The input terminal 5 is coupled to a first input terminal of a multiplier 10. An output terminal of the multiplier 10 is coupled to respective input terminals of a delay circuit 12 and a Hilbert filter 14. An output terminal of the delay circuit 10 is coupled to the real input terminal R of the first complex input terminal of a complex multiplier 22. An output terminal of the Hilbert filter 14 is coupled to an imaginary input terminal I of the first complex input terminal of the complex multiplier 22. (The real and imaginary components of a signal are sometimes termed in-phase, and ‘quadrature’ components, respectively, referring to their correspondence to components in some complex modulation schemes.) A real output terminal R of the complex output terminal of the complex multiplier 22 is coupled to an output terminal 15. The output terminal 15 generates the real portion of a phase-corrected received signal. The output terminal 15 may be coupled to a receiver back end (not shown). The receiver back end may include, for example, a trellis decoder, a Reed-Solomon decoder, a descrambler, and video, audio and auxiliary signal processors, all of known design. This receiver back end operates to generate an image represented by the transmitted HDTV video signal, and sound represented by the transmitted audio signal, all in a known manner.
The real output terminal R of the complex multiplier 22 is also coupled to an input terminal of a slicer 24 and a real first input terminal R of a phase detector/accumulator 26. An imaginary output terminal I of the complex output terminal of the complex multiplier 22 is coupled to an imaginary first input terminal I of the phase detector/accumulator 26. An output terminal of the slicer 24 is coupled to a real second input terminal R of the phase detector 26. At each symbol time, the slicer selects, from a programmed look up table, a data symbol corresponding to the point in the symbol constellation that is closest to the input symbol sample as its decision. That is, the slicer selects as its decision the symbol in its alphabet which is closest in Euclidean distance to the input symbol sample. More specifically, the slicer expects an input signal at predetermined signal points along the real axis corresponding to the transmitted symbols.
An output terminal of the phase detector/accumulator 26 produces a signal φE, representing the estimated phase error between the phase of a selected ideal signal and that of the corresponding received phase adjusted signal, as described above, and is coupled to an input terminal of a sine/cosine generator 28. Respective real R and imaginary I output terminals of the sine/cosine generator 28 are coupled to corresponding input terminals of a second complex input terminal of the complex multiplier 22. The combination of the complex multiplier 22, slicer 24, phase detector and accumulator 26 and sine/cosine generator 28 form a phase tracking loop 20.
In addition, phase tracking loops may have a parallel automatic gain control (AGC) loop, which corrects the signal for gain, to ensure that after the phase correction, the signal levels correspond to the predetermined slicer levels. The real output terminal of the complex multiplier 22 is also coupled to a first input terminal of an AGC detector and accumulator 16. The output terminal of the slicer 24 is coupled to a second input terminal of the AGC detector and accumulator 16. An output terminal of the AGC detector and accumulator 16 is coupled to a second input terminal of the multiplier 10, which performs the gain correction.
In operation, the VSB signal at the input terminal 5 has only a real component. However, in order to properly control the phase of the input signal IN, it must be rotated in the complex plane. The Hilbert filter 14 estimates an imaginary component I which corresponds to the real component R of the input signal IN. The delay circuit 12 compensates for the delay introduced by the Hilbert filter 14.
The complex input signal, represented by the real (R) and estimated imaginary (I) components, is derotated by the action of the complex multiplier 22. The real (R) component of the phase adjusted (derotated) signal, from the real output terminal of the complex multiplier 22, is supplied to the output terminal 15.
The slicer 24 compares the value of the real (R) component of the derotated signal to the ideal values of the real component for all of the possible symbols. The slicer 24 selects as the received symbol the symbol having an ideal real value closest to the real value of the derotated signal. The slicer 24 produces at its output terminal a signal having the value of the ideal real component of the selected symbol.
The phase detector and accumulator 26 generates a phase error signal φE by first estimating the phase angle between the ideal symbol from the slicer 24 and the corresponding output signal from the complex multiplier 22 in the complex plane. This phase difference is accumulated and the accumulation used as the phase error φE. The accumulator is also referred to as a numerically controlled oscillator (NCO) and used to accumulate the phase-error. As each phase difference is calculated, it is added to the previously calculated accumulation within the NCO and the total used as the phase error φE.
Complex real (R) and imaginary (I) components representing a phase correction angle for this phase error signal φE are generated in the sine/cosine generator 28. The amount of rotation of the input signal IN induced by the complex multiplier 22 is controlled by the values of these real (R) and imaginary (I) signals. The combination of the phase detector and accumulator 26 and sine/cosine generator 28 operate as a phase adjusting element. The complex multiplier 22 rotates the input signal IN by the compensating angle to produce the derotated output signal OUT.
Simultaneously, The AGC detector and accumulator 16 computes the amplitude difference between the actual derotated real component from the complex multiplier 22 and the ideal real component from the slicer 24. This difference represents the amount of error in the amplitude of the output signal OUT. This difference is accumulated and the accumulation used to control the multiplier 10 to adjust the gain of the input signal IN toward the desired level.
By providing fine control of the amplitude and phase of the input signal IN in this manner, the phase of the output signal OUT may be properly aligned with the transmitter carrier phase and the symbols may be detected in a more accurate manner.
One problem with this prior art system is that its design assumed that the phase had been adjusted relatively closely by the CTL. Thus, the sine/cosine generator 28 includes only values for adjusting the phase of the output signal OUT within a predetermined phase distance from zero. In one embodiment of such a prior art system, the sine/cosine generator 28 includes look-up tables which provide values for phase errors of only ±30°. Consequently, the maximum value from the NCO in the phase detector and accumulator 26 is adjusted to correspond to +30° while the minimum value from the NCO is adjusted to correspond to −30°. That is, the NCO in the phase detector and accumulator 26 is not allowed to have a wrap-around phase capability (±180°). Should the NCO wrap around from its maximum value to its minimum value, the correction phase skips from +30° to −30°. This represents a large phase discontinuity (around 300°), which, unless forbidden by design, is then detected as a large phase error and added to the accumulator (NCO). As a result, impulse noise and transient conditions in preceding circuit elements, such as the carrier tracking loop, symbol timing loop and equalizer, may cause substantial phase errors to accumulate in the phase detector and accumulator 26. This, in turn, may cause inaccurate and undesirable upper and/or lower limited phase outputs at the ±30° points or, if not forbidden, an NCO wrap-around, that is, a large phase discontinuity. In both cases, recovery of the phase tracker from these situations is almost impossible if the NCO is not reset to 0. A phase tracking system which provides full phase wrap-around capabilities, thus avoiding the problems related to impulse noise and transient conditions, permitting an easier self-recovery, is desirable.